UDP Receive engine Core
 
    Description

The MVD UDP Receive engine core is a drop-in module that includes the following functions :
  • Full hardware UDP extraction
  • Full hardware IP extraction
  • Different programmable filters on protocol fields
  • IP fragmentation not supported
  • Directly connectable with the XILINX TEMAC
  • Programmable with a Microblaze or a PPC405
  • Up to 450 Mbits/secDesign up to 125 MHz for Virtex-4/5

MVD can also provide additional remote or on-site support or cores for UDP Tx, ARP, ICMP, DHCP

    
             
    Features

Reception side Udp / Ip / Mac stack, a real time UDP offload engine

  • Drop-in module for Virtex-5, Virtex-4
  • Programmable filter for broadcast
  • Programmable filter for IP source/destination address
  • Programmable filter for UDP destination port
  • Different fields available in registers
  • Support JUMBO frame in option
  • Clock up to 125 MHz for Virtex-4/5
  • Netlist version available for ISE 8.2 and later
    
           
    Applications

MVD Hw UDP stack may be used in applications related to Ethernet reception, especially with XILINX FPGA technology		    
           
       

   
                       
      Documentation

    Contacts

Sales contact : info_cores@mvd-fpga.com
Technical support : support_cores@mvd-fpga.com