• Pipeline basics
• 603e pipeline implementation
• Execution model
• Execution serialization
• Branch management : static prediction
• Guarded memory

L1 CACHES

• Cache basics
• Cache related page / block attributes
• 603e L1 cache
• Software L1 data cache flush
• Cache coherency basics
• The MEI 3-bit L1 data line state
• MEI snooping sequences involving a 603e and a PCI master

INTERNAL DATA FLOWS

• The interface buffers
• The BIU [Bus Interface Unit]
• Sync and eieio instructions

603e SPECIFIC UNITS

• The 3 architecture layers introduction : UISA, VEA and OEA
• Low power modes
• JTAG debugger, hardware breakpoint vs software breakpoints
• Real time trace building using a logic analyser, the WindRiver solution

THE UISA LAYER

• Branch instructions
• Integer load / store instructions
• Integer arithmetic and logic instructions
• IEEE754 basics
• Float load / store instructions
• Float arithmetic instructions
• The EABI
• Code and data sections, small data areas benefits

THE VEA LAYER

• WIMG attribute bits
• Cache related instructions
• PowerPC timers : TB and DEC

THE OEA LAYER - MMU

• MMU goals
• The PowerPC address processing
• WIMG attributes definition
• Process protection through VSID selection
• TLB organization
• Page translation
• MMU implementation in real-time sensitive applications

THE OEA LAYER – EXCEPTION MECHANISM

• Exception state saving and restoring through SRR0/SRR1 registers
• Exception management : handler table, MSR update, automatic interrupt masking
• Recoverable vs non recoverable interrupts
• Requirements to support exception nesting

603e HARDWARE IMPLEMENTATION