INTRODUCTION TO DIGITAL SIGNAL PROCESSING

• Arithmetic processing of real-time signals
• Filtering, convolution, correlation
• Modified dual Harvard architecture
• DSP 568XX family introduction, compatibility with 5600X DSPs
• Introduction of motor types

563XX ARCHITECTURE

• Core busses
• Processing states
• Reset, low voltage, stop and wait operations
• 56807 mapping

THE DSP CORE

• The Data ALU
• The Address Generation Unit
• The Program Control Unit
• The instruction set
• C-to-assembly interface
• Software techniques
• Exception management
• The interrupt routing performed by the ICTN
• The debugging support
• JTAG use to access the OnCE
• The embedded flash memory
• Program sequence
• Erase sequence

HARDWARE IMPLEMENTATION

• On chip clock synthesis
• Wait state X data memory
• Wait state program memory

THE QUAD TIMER MODULE

• Timer module pinout
• Operating modes
• OFLAG output signal

THE ADCs

• Timing, pipelining
• Conversion sequence definition
• Synchronization to the PWM
• Optional sample correction

THE QUADRATURE DECODERS

• Quadrature decoders pinout
• Configurable digital filters
• Watchdog timer implementation

THE PULSE WIDTH MODULATORS

• Independent or complementary channel operation
• Deadtime generators
• IFault protection

THE SCI AND THE SPI MODULES

• SCI block diagram, IO signals
• Asynchronous vs synchronous operation modes
• Baud rate selection
• Bootstrap loading from the SCI
• Asynchronous transmit and receive sequences
• SPI synchronous communications basics
• Master vs slave selection
• Polarity selection

THE FLEXCAN CONTROLLER