Formation - Bridge PCI Tsi107 (anciennement MPC107) (reference 002605A)
 
        This is an on-site only course.    
           
    Partners
  • Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
  • Practical exercices are built with Diab Data compiler, downloaded on a Windriver HSI MPC7400 / MPC107 board through the EST probe
  • VisionClick debugger is used to control code execution
   
           
    Related Trainings
  • The 60X bus is explained in PowerPC CPU trainings : 603e (ref 002581A), 7XX (ref 002582A), 7400/10 (ref 002586A), 744X/5X (ref 002587A), MPC826X (ref 002589A)
  • The training called 002596A covers PCI bus
  • MVD also delivers training courses around embeded OS which can be useful : Embeded Linux, OSEK
   
           
    Prerequisites
  • PCI knowledge and 60X bus knowledge are mandatory
   
             
  Course Objectives
  • The course details Tsi107 internal datapaths
  • The I2O synchronization mechanism is studied
  • SDRAM timing parameters initialization is described
  • The training explains how to use the DMA controller to transfer data from SDRAM to PCI space
   
           
    Duration
  • 2-day course
   
           
    Topics

(The full description of this course can be provided on request)

Tsi107 OVERVIEW

  • Clock generation, DLL benefits
  • Memory mapping
  • Explanation of the translation mechanism to access PCI MEM space
  • Explanation of the translation mechanism used when PCI masters access the local SDRAM

THE SDRAM CONTROLLER

  • SDRAM basics
  • Mode register initialization
  • Command truth table
  • Tsi107 memory controller introduction
  • Address multiplexing
  • The Flash EPROM controller
  • X-port advantages and restrictions

THE PCI INTERFACE

  • Commands supported when the Tsi107 is PCI master
  • Commands supported when the Tsi107 is PCI target
  • Configuration space access through CONFIG_ADDRESS and CONFIG_DATA registers

THE 60X INTERFACE

  • 7XX or 74XX PowerPC connection
  • 60X slave connection
  • Error management

THE INTERRUPT CONTROLLER

  • EPIC operation modes
  • Interrupt request time-multiplexing
  • Interrupt nesting requirements
  • Integrated timers
  • Doorbell registers
  • I2O specification basics, synchronization by messages

THE DMA CONTROLLER

  • Direct mode vs chained buffer mode
  • Programming model
  • Transfer descriptor initialization when the scatter / gather mode is selected

THE I2C CONTROLLER

  • I2C basics
  • Interrupt driven communication sequence

RESET

  • Configuration pins sampling upon reset
  • Initialization sequence
   
           
    Documentation

Training manuals will be given to participants during training. Precise and easy of use, those notes can be used as a reference afterwards.
   
           
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