• Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
• This training course is approved by Xilinx

• This course covers advanced use of Xilinx tools and FPGAs. Some of the topics include: scripting, floorplanning, interactive probing of internal signals, proper coding, use of Virtex™-II high speed I/O, using FPGA Editor, I/O location constraints, creating RPMs (Relationally Placed Macros), and detailed coverage of the newest Xilinx FPGAs.

• Xilinx Optimisation des performances, ISE (ref. 002833A) course

• Xilinx Conception de FPGA - Principes de base (Ref. 002832A) course
• Xilinx Optimisation des performances, ISE5 (ref. 002833A) course
• Intermediate knowledge of VHDL or Verilog
• One or more years' experience with Xilinx tools and FPGAs

• Improve device performance and utilization while increasing productivity with Xilinx software and hardware

After completing this training, you will be able to :

• Take advantage of Xilinx tools' scripting capabilities
• Create and edit constraints for hand placing logic and creating timing constraints
• Create RPMs for improved performance of critical paths
• Decrease run-time through the use of Incremental Design Techniques
• Use the Floorplanner to create effective layouts of your design and decrease Place and Route run-times
• Take advantage of the Virtex-II architecture through increased knowledge of I/O layout, high-speed I/O, and clock design
• Make changes to a post-place and route design in the FPGA Editor for more efficient in-circuit testing

• 2-day course

(The full description of this course can be provided on request)

TRAINING OUTLINE

• Introduction
• Advanced Control Through Scripting
  • Command Line Implementation
  • UCF Editing
  • Lab 1: UCF and Scripting
  • Creating your Own RPM
  • Lab 2: RPM
• Reduce Debug Time
  • FPGA Editor: Viewing and Editing a Routed Design
  • Lab 3: FPGA Editor
• Improve Your Timing - Handcrafting Performance
  • Incremental Design Techniques
  • Floorplanner: Effective Layout
  • Lab 4: Incremental Design
• Optimize Your Design for Xilinx Architecture
  • High Speed I/O
  • Advanced Virtex-II Architecture and Design
  • Lab 5: Clock Design

LAB DESCRIPTIONS

• Lab 1- UCF and Scripting: Write constraints directly into a UCF file. Write program commands into a batch file to implement the design. Finally, modify the constraint values and program switches to obtain the greatest possible performance from the design.
• Lab 2 - RPM: Create an RPM in a UCF file. Use the Timing Analyzer to find a path that is not meeting timing constraints and identify the components of that path. Finally, RLOC the components to create the RPM and improve timing for that path.
• Lab 3 - FPGA Editor: Use the FPGA Editor to view and edit the correlate and accumulate design. Analyze the contents of a CLB; add a probe; remove, place, and modify components, and analyze long nets.
• Lab 4 - Incremental Design: Use incremental design techniques to gain faster turnaround times when you make changes to a module.
• Lab 5 - Clock Design: Use the global clock buffers correctly to create up to 16 different clocks. Use 16 "global" clocks and try to minimize the skew on these clock signals.