• Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
• This training course is approved by Xilinx

• This course is intended to provide intensive training on designing with the Xilinx PCI Core in your system. You will learn the basics of Xilinx PCI cores including PCI 64/66 Virtex, PCI 32, Spartan XL, Virtex-II. You will also learn design concepts and basic verification strategies for a PCI system design. The class includes labs where you get hands-on experience using the Xilinx PCI cores the Model Technology Simulator (Modelsim).

• For training on the PCI-X Addendum to the PCI Local Bus Specification and a detailed investigation into the operation of the PCI-X LogiCORE, take the Xilinx Conception pour bus PCI-X (Ref. 002842A) course.

• A good knowledge of PCI
• Working experience with digital design
• Basic knowledge of Verilog or VHDL
• Working experience with Xilinx Foundation and FPGA Express including writing UCF files

• Reduce design verification time
• Learn PCI design tips and tricks
• Reduce the risk of missing your deadline
• Significant time-to-market advantage

After completing this training, you will be able to :

• Identify guidelines for using PCI electrical and timing specifications
• Explain the operation of the Xilinx PCI LogiCORE
• Describe the User Configuration Module
• Show how Xilinx represents PCI signals
• Differentiate between the responsibilities of the PCI CORE and the User Application
• Identify functions and characteristics of Target and Initiator User Application signals
• Illustrate different Read/Write PCI transaction waveforms
• Design FIFOs that are able to communicate properly with PCI
• Describe how to design a target and initiator engine
• Describe the major concepts involved in designing a reusable testbench
• Identify general testbench methodologies
• Identify strategies for designing 64-bit applications
• Describe design considerations for 66 MHz PCI

• 2-day course

(The full description of this course can be provided on request)

TRAINING OUTLINE

• Course Intro
• Review of PCI Basics
• Introducing the Xilinx PCI LogiCORE Interface
• User Application Interface for Target
• User Application Interface for Initiator
• Electrical and Timing Specifications
• Designing FIFOs for Xilinx PCI
• Designing a Target Engine
• Lab 1: Analyzing PCI Bus Transactions
• Designing an Initiator Engine
• Lab 2: Understanding DMA Controller Transactions
• Handling Configuration Transactions
• Review of Day One
• Testbench Design and Verification
• Xilinx PCI 64 Bit and 66 MHz
• PCI Variations

LAB DESCRIPTIONS

• Lab 1 - Xilinx Tool Flow: Create a new project in the ISE Project Navigator and utilize the Architecture Wizard and PACE tool in the design process.
• Lab 1: Analyzing PCI Bus Transactions: This lab demonstrates typical PCI bus transactions and the signals associated with each type of bus transaction. The relationship between various signals is identified. Various settings are changed and the behaviors are analyzed after each change is made.
• Lab 2: Understanding DMA Controller Transactions: This lab demonstrates typical PCI bus transactions and the signals associated with each type of bus transaction. The relationship between various signals is identified.