Formation - Conception avec les transceivers RocketIO Multi-Gigabit (reference 002843A)
 
    Partners
  • Do not hesitate to request the detailed course description by contacting training@mvd-fpga.com
  • This training course is approved by Xilinx
  • The ModelSim simulator is used to simulate the MultiGigaBit Transceivers
    
           
        Related trainings
  • To fully cover the Virtex-II Pro technology, several training modules have been developed : CoreConnect (course 002585A), Virtex-II (course 002572A) and PPC405 (course 002630A)
  • The RapidIO course (reference 002602A) may be recommended to persons involved in a RapidIO design
    
           
    Prerequisites
  • Knowledge of Virtex-II and VHDL is mandatory
    
           
  Course Objectives
  • Through several practical labs, the attendee becomes familiar with the RocketIO MGTs
  • The course explains how the clock correction logic compensates for frequency difference between TX and RX clocks
  • Channel bonding is detailed
  • This course shows how to use the architecture wizard to instantiate quickly RocketIO primitives
    
           
    Duration
  • 2-day course
    
           
    Topics

(The full description of this course can be provided on request)

INTRODUCTION TO MULTIGIGABIT TRANSCEIVERS

  • Block diagram
  • Support for various high speed protocols
  • Ports and attributes

CLOCKING AND RESETS

  • Reference clocks, SERDES_10B attribute
  • Recommended clock oscillators
  • User clocks
  • Resets

8B / 10B DETAILS

  • Code-group generation
  • DC balance, runtime disparity calculation and checking
  • Control characters, code group delimitation through commas
  • Idle sequences
  • Encoder and decoder ports and attributes

COMMAS AND COMMA ALIGNMENT

  • Comma alignment port and attributes
  • RXCHARISCOMMA vs RXCOMMADET
  • User-defined comma example
  • Word alignment

CRC

  • CRC algorithm built into the RocketIO MGTs
  • User-mode CRC
  • CRC and Fibre Channel EOP

CLOCK CORRECTION

  • Rx elastic buffer
  • Clock correction example
  • Definition of the correction sequence

CHANNEL BONDING

  • Channel bonding ports and attributes
  • Allowable channel skew
  • Masters and slaves
  • Channel bond wait and offset

PMA OVERVIEW

  • PLL characteristics
  • Power filtering
  • PCB considerations, DC and AC coupling
  • Pre-emphasis
  • Loopback modes
  • System design, analog simulation tools, HSPICE models

ARCHITECTURE WIZARD

  • Using the architecture wizard
  • Output files
  • HDL source file example
  • UCF file

IMPLEMENTING A ROCKET IO DESIGN

  • Latency through transceiver block
  • Transceiver placement for channel bonding
  • Timing constraints
  • Software flow, design entry, attribute passing, HDL simulation
  • FPGA editor

STANDARD COMPLIANCE ISSUES

  • Gigabit Ethernet compliance
  • 10-gigabit Ethernet with XAUI interface compliance
  • PCI express compilance
  • RapidIO compliance
  • Fibre Channel compliance
  • Serial ATA compliance
  • Infiniband compliance

IP OVERVIEW : AURORA

  • Aurora backplane protocol
  • Easy implementation
  • Settable and controllable features
  • Reset and power down

IP OVERVIEW : PCI EXPRESS

  • Layers, packet flow
  • PCI express logicore architecture
  • Attributes
  • Serial bitstream
    
           
    Documentation

Training manuals will be given to participants during training. Precise and easy of use, those notes can be used as a reference afterwards. 		   
           
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If you want to know our other training courses and their contents, you can consult or download our complete training courses list on this page : Training courses - General presentation