• Internal data flows, OCEAN switch fabric, packet reordering
  Implementation examples
  Address map, ATMU, OCEAN configuration
  Local vs external address spaces, inbound and outbound address decoding
  Accessing memory-mapped registers from external master
  

THE e500 CORE [30-hour]

THE INSTRUCTION PIPELINE [2-hour]

• Dual-issue superscalar control, out-of-order execution, 12-entry instruction queue, 14-entry completion queue
• Execution units : 2 simple Integer Units + 1 Complex Integer Unit
• Dynamic branch prediction using a 128-set 4-way set associative Branch Target Buffer
• Execution timing, rename register operation, instruction serialization, instruction scheduling guidelines

DATA AND INSTRUCTION PATHS [2-hour]

• The Core Complex Bus : high speed on-chip local bus with data tagging
• Load store unit, data buffering between LSU and CCB
• The LMQ, the store queue, the castout queue
• Store miss merging and store gathering
• Memory access ordering
• Lock acquisition and import barriers

THE MEMORY MANAGEMENT UNITS [6-hour]

• Thread vs process
• The first level MMU and the second level MMU, consistency between L1 and L2 TLBs
• Snooping of TLBs
• TLB software reload, page attributes WIMGE
• Process protection, variable number of PID registers and sharing
• MPC8548E 36-bit real addressing
• MMU implementation in real-time sensitive applications

CACHES [4-hour]

• The L1 caches, PLRU replacement algorithm, 8-way set associativity, cache block and unlock APU
• Cache coherency : MEI vs MESI state machine
• Level 2 cache, partition into L2 cache plus SRAM
• Allocation of data transferred by external masters into the cache : stashing
• e500 coherency module

PROGRAMMING [4-hour]

• Differences between the new Book E architecture and the classic PowerPC architecture
• Floating Point units, Double-Precision FP of MPC8548E
• Signal Processing APU (SPU) : implementation of the SIMD capability without using a separate unit
• PowerPC EABI : sections, C-to-assembly interface

EXCEPTIONS [4-hour]

• Book E exception handling
• Critical versus non critical
• Handler table
• Syndrome registers updating when an exception is taken, specific machine check interrupt, exception nesting, recoverability from interrupt, soft stop
• Core timers : Decrementer, Time Base, Fixed Interval Timer and Software Watchdog
• Configurable context switching for GPRs, SPRs and some additional registers

DEBUGGING [2-hour]

• Performance monitoring, counting of events
• JTAG emulation, real time trace when the e500 core executes cached instructions
• Watchpoint logic, triggering capabilities based on user programmable events

THE PLATFORM OPERATION [46-hour or 40-hour with or without PCI Express]

RESET, CLOCKING AND INITIALIZATION [4-hour]

• Platform clock
• RapidIO transmit clock source selection
• Power-on reset sequence, using the I2C interface to access serial ROM
• Power-on reset configuration
• Boot page translation
• Power management

MPC840/MPC8541E DDR1 SDRAM CONTROLLER [6-hour]

• DDR-SDRAM operation : a 256-Mb DDR-SDRAM from Micron is used as an example
• Jedec specification basics, mode register initialization, bank selection and precharge
• Command truth table
• Hardware interface
• Refresh types
• Bank activation, read, write and precharge timing diagrams, page mode
• ECC error correction
• DDR-SDRAM controller introduction
• Initial configuration following Power-on-Reset
• Address decode
• Timing parameters programming
• Initialization routine

MPC8548E DDR2 SDRAM MEMORY CONTROLLER [6-hour]

• DDR2 operation
• Jedec specification basics, mode register initialization, bank selection and precharge
• Command truth table
• Hardware interface
• Refresh types
• Bank activation, read, write and precharge timing diagrams, page mode
• ECC error correction
• Introduction to the DDR-SDRAM controller
• Initial configuration following Power-on-Reset
• Address decode
• Timing parameters programming
• Initialization routine
• FCRAM interface commands

LOCAL BUS CONTROLLER [2-hour]

• Multiplexed 32-bit address and data transfers
• Burst support
• Dynamic bus sizing
• GPCM, UPMs and SDR SDRAM states machines

MPC8540/MPC8541 PARALLEL RapidIO INTERFACE UNIT [6-hour]

• 8-pin parallel interface, LVDS signalling
• Reordering across priority levels
• Packet pacing support at the physical layer
• Atomic operations
• RapidIO compliant message unit

MPC8548E SERIAL RapidIO INTERFACE [6-hour]

• RapidIO port
• Message Unit, direct vs chaining mode operation
• RapidIO doorbell and port-write unit
• Accessing configuration registers via RapidIO packets
• Programming inbound and outbound ATMUs
• Hot-swap support
• Error handling

PCI EXPRESS INTERFACE [6-hour]

• MPC8548E 8-lane PCI Express interface
• Modes of operation, Root Complex / Endpoint
• Byte swapping
• Transaction ordering rules
• Programming inbound and outbound ATMUs
• Configuration, initialization

PCI/PCI-X FUNCTIONAL UNITS [6-hour]

• Bridge features
• Data flows : Read prefetch and write posting FIFOs
• Inbound transactions handling, Outbound transactions handling in both modes
• Support of multiple split transactions in PCI-X mode
• PCI-to-memory and memory-to-PCI streaming
• PCI/PCI-X possible combinations for MPC8540, MPC8541E and MPC8548E

INTEGRATED DMA CONTROLLER [2-hour]

• Priority between the 4 channels
• Support for cascading descriptor chains
• Scatter / gathering
• Selectable hardware enforced coherency
• Ability to start DMA from external 3-pin interface

PERFORMANCE MONITOR AND DEBUG FEATURES [2-hour]

• Event counting
• Threshold events
• Chaining, triggering
• Watchpoint facility
• Trace buffer
• DDR SDRAM interface debug
• Local bus interface debug

INTEGRATED PERIPHERALS [10-hour]

THE ETHERNET CONTROLLERS [6-hour]

• 802.3 specification fundamentals : the 3 layers PHY, MAC and control
• Frame format with and without VLAN option
• IEEE 802.3, 802.3u, 820.3x, 802.3ac compliance
• Address recognition, pattern matching
• MII interface
• Buffer descriptors management
• the three-speed Ethernet controllers (TSECs)
• Physical interfaces : GMII, MII, TBI or RGMII
• Buffer descriptor management
• Layer 2 acceleration accept or reject on address or pattern match
• 256-entry hash table for unicast and multicast
• Direct queuing of four flows
• MPC8548E management of VLAN tags and priority, VLAN insertion and deletion
• MPC8548E quality of service
• MPC8548E FIFO mode

SECURITY ENGINE [2-hour]

• Overview of the encryption mechanism
• Introduction to DES and 3DES algorithms
• Data packet descriptors
• Crypto channels
• Link tables
• ping by caches
• MPC8458 XOR acceleration

LOW SPEED PERIPHERALS [2-hour]

• Programmable Interrupt Controller
• Open PIC architecture compatibility
• Interrupt nesting
• Description of the 4 timers / counters
• Message interrupts
• Introduction to UART protocol
• Description of the NS16450/16550 compliant Uarts
• Bit rate programming
• Flow control signal management
• I2C protocol fundamentals : addressing, multimaster operation
• Transfer timing diagrams, SCL and SDA pins
• Transmit and receive sequence

MPC8541E - COMMUNICATION PROCESSOR MODULE [18-hour]

INTRODUCTION TO CPM [2-hour]

• CP operation : peripheral prioritization
• Command register
• DPRAM organization
• Parallel ports
• Generic timers
• IDMA vs SDMA

THE SERIAL INTERFACE [2-hour]

• NMSI versus TDM
• MCC connection to SI
• Supported protocols and max data rate
• Transmit and receive clock selection
• Baud rate generators
• Communication initialization sequence
• Buffer descriptor ring allocation in DPRAM
• Buffer chaining
• Interrupt management

THE MULTI CHANNEL CONTROLLERS [2-hour]

• DPRAM organization
• Time slot vs logic channel
• Super channels
• HDLC channel parameters
• Interrupt queues

THE SERIAL COMMUNICATION CONTROLLERS [2-hour]

• Data encoding /decoding selection
• Hardware flow management
• UART on SCC : inserting control characters into the transmit data stream
• HDLC on SCC
• Ethernet on SCC : address recognition, hash table programming

FAST ETHERNET CONTROLLER [2-hour]

• 802.3u basics
• MII interface
• Hash tables utility
• Parameter RAM description
• BD description

ATM BASICS [1-hour]

• Main features
• ATM benefit compared to X.25 or ISDN
• Standardization and related links
• UNI and NNI network interfaces
• Cell format
• Virtual connection
• Layer model
• AAL1 layer : circuit emulation
• AAL3/4 : used by the service providers
• AAL5 : packet transfer
• ATM addresses
• Connection establishment

ATM TRAFFIC MANAGEMENT [1-hour]

• The 5 service classes defined by the ATM forum : CBR, VBRrt, VBRnrt, UBR, ABR
• The QoS ATM attributes : PCR/CDVT, CLR, CTD/CDV
• Traffic policy
• Traffic shaping
• Early packet discard

THE MPC8541E ATM CONTROLLER [6-hour]