INTRODUCTION TO THE MPC8560

• Internal data flows, OCEAN switch fabric, packet reordering
• Address map, ATMU
• Local vs external address spaces, inbound and outbound address decoding
• Accessing CCSR memory from external master

THE e500 CORE

• The instruction pipeline
• Dynamic branch prediction
• The first level MMU and the second level MMU
• Process protection
• The L1 caches
• Level 2 cache
• e500 coherency module
• Load store unit, data buffering between LSU and CCB
• Signal Processing APU (SPU)
• PowerPC EABI
• Book E exception handling
• Power management
• JTAG emulation

RESET, CLOCKING AND INITIALIZATION

• Platform clock
• Power-on reset sequence, use of the I2C interface to access serial ROM
• Boot page translation
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BASICS OF HARDWARE IMPLEMENTATION

• DDR-SDRAM controller
• Local bus controller
• RapidIO interface unit
• PCI/PCI-X functional unit
• Software implementation of these units

LOW SPEED PERIPHERALS

• Programmable Interrupt Controller
• Interrupt nesting
• Description of the 4 timers / counters
• Message interrupts
• I2C controller

THE THREE-SPEED ETHERNET CONTROLLERS TSECs

• Physical interfaces : GMII, MII, TBI or RGMII
• Buffer descriptor management
• Layer 2 acceleration accept or reject on address or pattern match
• 256-entry hash table for unicast and multicast
• Direct queuing of four flows

INTEGRATED DMA CONTROLLER

• Priority between the 4 channels
• Scatter / gathering
• Selectable hardware enforced coherency

CPM INTRODUCTION

• CP operation : peripheral prioritization
• Command register
• DPRAM organization
• IDMA vs SDMA

THE SERIAL INTERFACE

• NMSI versus TDM
• MCC connection to SI
• Baud rate generators
  Communication initialization sequence
• Buffer descriptor ring allocation in DPRAM
• Buffer chaining

THE MULTI CHANNEL CONTROLLERS

• DPRAM organization
• Time slot vs logic channel
• Super channels
• HDLC channel parameters
• Interrupt queues

THE SERIAL COMMUNICATION CONTROLLERS

• Data encoding /decoding selection
• Hardware flow management
• HDLC on SCC
• Ethernet on SCC : address recognition, hash table programming

FAST ETHERNET CONTROLLER

• 802.3u basics
• MII interface
• Hash tables utility
• Parameter RAM description

ATM BASICS

• ATM benefit compared to X.25 or ISDN
• UNI and NNI network interfaces
• Cell format
• Virtual connection
• Layer model
• AAL1 layer : circuit emulation
• AAL3/4 : used by the service providers
• AAL5 : packet transfer
• Connection establishment

ATM TRAFFIC MANAGEMENT

• The 5 service classes defined by the ATM forum : CBR, VBRrt, VBRnrt, UBR, ABR
• The QoS ATM attributes : PCR/CDVT, CLR, CTD/CDV
• Traffic policy
• Traffic shaping

THE MPC826X ATM CONTROLLER