Formation - Le bus HyperTransport (reference 003153A)
 
    Related trainings
  • The PCI bus 2.3 course could be useful to understand the packet ordering rules as well as the configuration space (reference 002596A)
  • MVD also delivers training courses around embeded OS which can be useful : Embeded Linux, OSEK
    
           
    Prerequisites
  • Experience of a high speed digital bus like PCI or IEEE1394
    
             
  Course Objectives
  • Point-to-point interconnect benefits compared to shared busses are highlighted
  • The hardware implementation is described
  • The course focuses on the packet ordering rules
  • The course describes the discovery sequence required to initialize the HyperTransport chain
    
           
    Duration
  • 2-day course
    
           
    Topics

(The full description of this course can be provided on request)

OVERVIEW

  • Topology of a HyperTransport based board : cavern devices, tunnel devices and bridges
  • Point-to-point interconnect approach
  • Benefits of HyperTransport in comparison with PCI
  • Key features of HyperTransport protocol

THE HARDWARE INTERFACE

  • LVDS differential pairs
  • Double Data Rate clocking
  • Signal groups
  • Impedance requirements
  • Link transfer timing characteristics
  • Detailed transfer timing budget
  • FIFO sizing

LINK INITIALIZATION

  • PWROK and RESET# shared signals
  • IO chain initialization, finding the firmware ROM
  • Scalable performance
  • Determination of the link width
  • Link frequency initialization

PACKET STRUCTURE

  • Control packets : Request, Response and Information
  • Objective of the Flush and Fence packets
  • Data packets

TRANSFER PROTOCOL

  • Objectives of ordering rules
  • IO streams, host ordering requirements, downstream IO ordering
  • Virtual channels

FLOW CONTROL MECHANISM

  • Use of NOP packets
  • Insertion of information packets within data packets
  • Initialization and use of the counters

TRANSACTION EXAMPLES

  • Routing packets
  • Addressing, memory mapping
  • Transfer of a Read Request packet and associated Read Response packet
  • Transfer of a Posted Write packet
  • Transfer of a broadcast packet
  • Transfer of Flush and Fence packets
  • Boolean semaphore management

CONFIGURATION ACCESSES

  • Configuration type cycles, what is new compared to PCI
  • The HyperTransport structure present in the capability list
  • Use of these registers by the configuration software
  • System management, command mapping, special cycles
  • Interrupt management

DOUBLE-HOSTED CHAINS

  • Sharing double-hosted chain vs Non-Sharing double-hosted chains
  • Breaking the chain through software in the Non-sharing case

POWER MANAGEMENT

  • Reporting power management events to the host bridge
  • Signalling wakeup
  • Determination of upstream and downstream directions

ERROR DETECTION AND HANDLING

  • CRC calculated over 512 bit-times on link, CRC window
  • Error conditions
  • Error reporting
  • Sync flooding

ISOCHRONOUS TRAFFIC

  • Requirements for devices when they support isochronous packets
  • Isochronous flow control

THE EIGHTH-GENERATION OPTERON PROCESSOR FROM AMD

  • Integration of a DDR-SDRAM controller
  • Building a SMP platform through HyperTransport links
  • The AMD-8131 HyperTransport PCI-X tunnel
  • The AMD-8111 HyperTransport IO hub cave

TEST OF A HYPERTRANSPORT PLATFORM

  • Value provided by adding a connector into the design
  • Check lists for electrical and protocol compliance
  • PCB design considerations
  • Benefits of analysis probe through the FuturePlus solution
    
           
    Documentation

Training manuals will be given to participants during training. Precise and easy of use, those notes can be used as a reference afterwards. 		   
           
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If you want to know our other training courses and their contents, you can consult or download our complete training courses list on this page : Training courses - General presentation