INTRODUCTION TO MCF523X

• Coldfire roadmap
• 523X block diagram
• Pinout
• Memory mapped I/O organization

V2E CORE

• V2E pipeline
• Addressing modes
• Branch, data transfer, arithmetic, logic, shift & rotate, bit instructions
• Mac instructions, implementation of a fixed-point DFT
• C to assembly interface
• Section definition, parameterizing the linker command file
• Exception management
• Internal SRAM
• 523X cache operation
• Power management

DEBUG FACILITIES

• Intrusive vs non-intrusive debug
• BDM port
• Hardware breakpoints
• Trace port

RESET

• Reset sources
• Clocking
• Reset control flow
• Chip Configuration Module [CCM]
• Requirements of the boot routine

CENTRAL PERIPHERALS

• SCM
• The interrupt controller
• The Edge Port Module
• Watchdog timer module
• Programmable Interrupt Timer Modules

THE DMA CONTROLLER

• Channel prioritization
• Bandwidth control
• Transfer termination
• Utilization of DMA timers

HARDWARE IMPLEMENTATION

• Dynamic bus sizing
• Address decoding
• Data transfer sequence
• Burst cycles

THE MEMORY CONTROLLER AND THE SDRAM CONTROLLER

• The memory controller : SRAM/Flash connection, chip-select programming
• DRAM / SDRAM basics
• The 523X (S)DRAM controller : address decoding, refresh rate definition, address multiplexing selection

COMMUNICATION CONTROLLERS

• The UART Module
• The QSPI
• The I2C controller
• The FlexCAN controller
• The Fast Ethernet Controller

CRYPTOGRAPHY MODULES