• This training course is approved by Xilinx

• Learn how signal integrity techniques are applicable to high-speed interfaces between Xilinx FPGAs and semiconductor memories. This course teaches you about high-speed bus and clock design, including transmission line termination, loading, and jitter. You will work with IBIS models and complete simulations using CAD packages. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules and practical hands-on labs.

WHO SHOULD ATTEND ?

• Digital designers, board layout designers, or scientists, engineers, and technologists seeking to implement Xilinx solutions. Also end users of Xilinx products who want to understand how to implement high-speed interfaces without incurring the signal integrity problems related to timing, crosstalk, and overshoot or undershoot infractions.

• Xilinx FPGA design experience preferred

After completing this comprehensive training, you will have the necessary skills to :

• Identify when signal integrity is important and relevant
• Interpret an IBIS model and correct common errors
• Apply appropriate transmission line termination
• Understand the effect loading has on signal propagation
• Mitigate the impact of jitter
• Manage a memory data bus
• Understand the impact of selecting a PCB stackup
• Differentiate between on-chip termination and discrete termination

• 2-day course

Course Outline

Day 1

• Introduction
• Transmission Lines
• Mentor or Cadence Lab 1
• IBIS Models
• Mentor or Cadence Lab 2
• Mentor or Cadence Lab 3
• High-Speed Clock Design
• Mentor or Cadence Lab 4
• SRAM Requirements
• Mentor or Cadence Lab 5

Day 2

• Physical PCB Structure
• On-Chip Termination
• SDRAM Design
• Mentor Lab 6
• Managing an Entire Design

Lab description

• Mentor Lab 1: Opening the appropriate Mentor simulator
• Mentor Lab 2: Hands-on signal integrity observation of reflection and propagation effects
• Mentor Lab 3: Using an IBIS simulator to study basic transmission line effects
• Mentor Lab 4: Using saved simulation information to perform power calculation. Also, additional clock simulations
• Mentor Lab 5: Observing the effects of coupling on transmission lines
• Mentor Lab 6: Demonstrating how an SDRAM module can behandled with an EBD model
• Cadence Lab 1: Opening the appropriate Cadence simulator
• Cadence Lab 2: Analysis of a simple clock net
• Cadence Lab 3: Signal integrity effects caused by multidrop clock networks
• Cadence Lab 4: Crosstalk analysis
• Cadence Lab 5: Address and data analysis