• This training course is approved by Xilinx

• Interested in learning how to effectively utilize Virtex-4 ^TM architectural resources? This course focuses on understanding as well as utilizing several of the new and enhanced resources found in our newest device. Topics covered include a Virtex-4 overview; the DCM and PMCD; global and regional clocking techniques; memory and FIFO; and, source synchronous resources. A combination of modules and labs allow for practical hands-on application of the principles taught in this course.

WHO SHOULD ATTEND ?

• Experienced Xilinx users, or those who have taken the Fundamentals of FPGA Design and Designing for Performance courses. Students should have a solid understanding of Virtex-II/Pro/X Xilinx FPGA architectures, the ISE software, timing constraints, and timing closure techniques.

• Fundamentals of FPGA Design
• Understanding of Virtex-II/Pro/X architecture
• Intermediate knowledge of VHDL or Verilog

After completing this comprehensive training, you will have the necessary skills to :

• Utilize Virtex-4 Global Clocking Resources
• Utilize Virtex-4 Regional Clocking Resources
• Design with the Virtex-4 DCM
• Design with the Virtex-4 PMCD
• Describe System Monitor Resources
• Discuss Virtex-4 BRAM and FIFO blocks
• Utilize the DSP48 block
• Explain source-synchronous resources

• 2-day course

Course Outline

Day 1

• Introduction
• Product Overview
• DCM Clock Management
• PMCD Clock Management
• Lab 1: Clock Management
• Clock Networks
• Lab 2: Clocking Techniques
• I/O and Source Synchronous Resources
• Lab 3: Utilizing Source Synchronous I/O

Day 2

• Day 2 Overview
• Block RAM Memory Resources
• FIFO Memory Resources
• Lab 4: Block RAM and FIFO
• XtremeDSP Slice
• Lab 5: FIR Filter
• Configuration
• Day 2 Review

Lab description

• Lab 1: Clock Management – Designing a clock management scheme using DCMs and PMCDs.
• Lab 2: Clocking Techniques – Utilizing global and regional clocknetworks.
• Lab 3: Utilizing Source Synchronous I/O Resources.
• Lab 4: Block RAM and FIFO – Utilizing new block RAM featuresand FIFO16 dedicated resource.
• Lab 5: FIR Filter – Utilizing the DSP48 block.