Formation - Bus Serial ATA II (reference 003523A)
 
    Partners
  • Timing diagrams are taken from a PC implementing a SATA interface thanks to the CATC Analyser board distributed by VSystems
    
           
    Related Trainings
  • MVD also delivers training courses around embeded OS which can be useful : Embeded Linux, OSEK
    
           
    Prerequisites
  • Experience of a high speed digital bus like PCI-X or IEEE1394 is recommanded
    
             
  Course Objectives
  • Packet switching benefits compared to shared busses are highlighted
    
           
    Duration
  • 2-day course
    
           
    Topics

ORIGINS OF THE SATA INTERFACE

  • Parallel ATA limitations
  • Serial ATA roadmap
  • Enhanced Integrated Drive Electronics (EIDE)
  • Faster HDD access and logical block addressing (LBA)
  • ATAPI for support of other peripheral devices
  • Programmed Input / output, direct memory access (UDMA)

SATA ARCHITECTURE

  • General overview, topology, connectivity
  • Architectural layering
  • Standard ATA emulation
  • Flow control

TRANSPORT LAYER

  • Frame and Frame Information Structure (FIS)
  • Host transport states
  • Device transport states

LINK LAYER

  • Transmission words
  • 8b/10b coding basics, clock recovery, code-group alignment
  • Framing concepts
  • Scrambling

PHYSICAL LAYER

  • Cable and connectors
  • Electrical signalling
  • Spread Spectrum Clocking
  • Link initialization
  • Elastic buffer
  • Power and signal lines

POWER MANAGEMENT

  • Interface power states
  • Power management primitives
  • Comwake signal sequence

HIGH LEVEL OPERATION

  • Device command layer protocol
  • Host adapter register interface
  • Error handling

TESTING AND VERIFICATION

  • Serial ATA analysers
  • Traffic capture
  • Test and verification of SATA devices
    
           
    Documentation

Training manuals will be given to participants during training. Precise and easy of use, those notes can be used as a reference afterwards. 		   
           
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