INTRODUCTION TO 440SPe

• Block diagram
• Internal bus organization : dual PLB, OPB, DCR
• Internal concurrent transfers examples
• Introduction to Integrated peripherals
• Hardware implementation
• 440SPe memory mapping
• Programming model

ON CHIP BUSES

• Introduction to CoreConnect
• 2-way PLB crossbar, programming
• Bus errors recovery from syndrome registers
• PLB performance monitor

THE PowerPC CORE

• Pipeline
• Internal caches
• Speculative loads, storage ordering and synchronization : msync & mbar instructions
• MMU

BOOK E COMPLIANT CORE

• Programming model
• Branch instructions
• Addressing modes, load & store instructions
• Integer instructions
• 16-bit mac instructions to develop DSP algorithms
• Exception management
• Exception priorities
• Core timers
• PowerPC EABI
• JTAG debug
• Real time trace

CLOCKS, RESET AND POWER MANAGEMENT

• Clocks synthesizer
• PCI-X clocking
• PCI Express clocking
• Clock and power management
• Low power modes
• Reset signals
• Initialization software requirements
• IIC bootstrap controller : processor configuration through the IIC port
• PCI-X bootstrap configuration
• Peripheral software reset
• Booting from local ROM in Host bridge mode
• Booting from local ROM in Agent bridge mode
• Booting from PCI

L2 CACHE CONTROLLER & INTERNAL SRAM CONTROLLER

• L2 cache features
• Data movement between memory, L2 and L1 caches
• L2 cache programming
• SRAM controller

INTERRUPT CONTROLLER & GENERAL PURPOSE TIMERS

• Interrupt masking and acknowledgement sequences
• Critical interrupt handlers using vectorization
• Interrupts priority management
• General Purpose Timers

THE DDR-SDRAM CONTROLLER

• DDR-SDRAM operation
• Jedec specification basics
• Hardware interface, SSTL-2 termination logic
• Differences between DDR-I and DDR-II
• ECC error correction
• Introduction to the 440SPe DDR-SDRAM controller
• Page management unit
• Initialization sequence
• Hardware implementation

THE EXTERNAL BUS CONTROLLER

• External bus pinout, driver enables
• Dynamic bus sizing
• Timing parameters
• Device-paced transfers

THE PCI-X BUS CONTROLLER

• DDR PCI-X operation
• Host vs agent configuration
• Data flows : Read prefetch and write posting buffers
• Inbound transactions handling, Outbound transactions handling
• Error handling
• Arbitration algorithm
• Boot modes, initialization / Reset sequence
• Sleep mode entering
• PCI-Express to PCI-X bridging
• Message passing
• Interrupts and MSI

THE PCI EXPRESS INTERFACES

• 8-lane host interface
• 4-lane secondary interfaces
• Root complex vs EndPoint configuration
• PCI Express functional cores
• Hardware implementation
• Power management
• Error handling
• Messaging

THE FAST ETHERNET CONTROLLER

• 802.3 specification fundamentals : PHY and MAC layers
• 440SPE Ethernet controller organization
• PHY
• Flow control
• VLAN support
• Frame filtering
• Hash table usage in switch applications
• Memory Access Layer controller, buffer management
• Buffer descriptors initialization
• Errors management

THE XOR ACCELERATOR UNIT

• Parity generation and check functions
• Command block list
• DMA capability

THE I2O MESSAGE UNIT / DMA CONTROLLER

• Message vs doorbell
• Management of inbound messages
• Management of outbound messages
• DMA operation

STANDARD PERIPHERALS