First day

THE ARM ARCHITECTURE

• ARM operation modes
• The ARM registers set, register organization summary according to the current mode
• Program Status Registers
• Exception handling, vector table, automatic switch into ARM mode
• Instruction sets

ARM11 CPU ARCHITECTURE

• ARM11 superscalar pipeline operation
• Dynamic vs static branch prediction
• Out of order execution
• Return stack

MEMORY SUBSYSTEMS

• Cache basics
• Hit under miss and its consequence : out of order abort
• ARM11 related instructions
• Highlighting data flows between main memory, L1 cache and L2 cache
• Tightly coupled memories
• Configuration & control through CP15

Second day

MEMORY MANAGEMENT & PROTECTION

• Introduction to page management
• V6 virtual memory architecture
• ARM V6 endianness
• Data alignment
• Memory Barriers

ARMv6 INSTRUCTION SET

• Additional classes of instruction
• Standard multiply extension
• Long multiplication
• Packed data types
• V6z NOP32 instruction to enter low power mode

PRIMECELL VECTORED INTERRUPT CONTROLLER

• Interrupt controllers
• Primecell VICs
• Reducing interrupt latency through automatic vector generation
• VIC basic signal timing
• Interrupt priority and masking

TRUSTZONE

• TrustZone conceptual view
• Secure to non secure permitted transitions
• Related CP15 registers

Third day

AHB PROTOCOL

• Transfers with AHB
• Use of HREADY, HRESP & HTRANS signals
• Implementation of indivisible transactions

AXI PROTOCOL

• Topology : direct connection, multi-master, multi-layer
• PL300 AXI interconnect
• AXI channels, channel handshake
• Support for unaligned data transfers
• Transaction ordering, out of order transaction completion
• Read and write burst timing diagrams

APB

• Address decoding stages
• APB interconnect
• APB in AMBA3

ARM11 DEBUG

• Basic debug requirements
• Embedded core debug
• DBGTAP interfacing

TRACING AN ARM11-BASED SYSTEM

• Motivation to real-time trace
• About core sight ETM11
• Tracing with core sight ETM11
• Implementing trace : ETB

Fourth day

ARM1176 OVERVIEW

• Block diagram
• AXI (AMBA3) interfaces
• ARM1176 example system
• Reset and clocking
• Booting

INTELLIGENT ENERGY MANAGER

• Conventional power management
• Clocking
• IEM infrastructure and components
• Energy management principles
• Switching voltage levels

LEVEL ONE AND LEVEL TWO MEMORY SYSTEMS

• TCM and cache interaction
• DMA channel
• Endianness
• Peripheral interface transfers
• AXI ports
• Implementation of the L220 level-2 cache controller

ARM11 MULTI-PROCESSOR SYNCHRONISATION