Highlighting data paths inside the MPC8360E
Block diagram : characteristics of each of the 3 internal modules e300 core, Platform, QuiccEngine
Software migration from MPC82XX/MPC85XX families

THE e300 CORE

THE INSTRUCTION PIPELINE

• e300 pipeline
• Branch processing unit
• Coding guidelines

DATA PATHS

• Load / store buffers
• Sync and eieio instructions
• Store gathering mechanism

CACHES

• Cache basics
• Cache locking
• L1 caches
• Cache coherency mechanism
• The MEI state machine
• Management of cache enabled pages shared with PCI DMAs
• Software enforced cache coherency
• Cache flush routine

SOFTWARE IMPLEMENTATION

• e300 registers
• addressing modes, load / store instructions
• IEEE754 basics, floating points numbers encoding
• Floating point load / store instructions
• Floating point arithmetical instructions
• The PowerPC EABI
• Linking an application with Diab Data, parameterizing the linker command file

THE MMU

• Thread vs process
• Real mode restrictions
• Memory attributes and access rights definition
• Virtual space benefit
• TLBs organization
• Segment-translation
• Page-translation
• MMU implementation in real-time sensitive applications

THE EXCEPTION MECHANISM

• Exception management mechanism
• Registers updating according to the exception cause
• Requirements to allow exception nesting

THE DEBUG PORT

• JTAG emulation, restrictions
• Hardware breakpoints
• Performance monitor

THE PLATFORM CONFIGURATION

POWER, RESET AND CLOCKING

• DC and AC electrical characteristics
• Configuration signals sampled at reset
• Reset configuration words source
• Utilization of the I2C boot sequencer
• PCI Host / Agent configuration
• Boot memory space
• Clocking in PCI Host mode, system clock domains
• External clock inputs

PLATFORM CONFIGURATION

• Address translation and mapping
• Arbiter and bus monitor
• General purpose inputs / outputs
• Timers
• Dynamic power management

THE DDR2 MEMORY CONTROLLER

• Jedec specification basics
• On-Die termination and calibration
• Differences between DDR1 and DDR2
• Command truth table
• Hardware interface
• ECC error correction
• DDR-SDRAM controller overview
• Address decode
• Timing parameters programming
• Initialization routine

LOCAL BUS CONTROLLER

• Multiplexed or non-multiplexed address and data buses
• Dynamic bus sizing
• GPCM, UPMs states machines

PCI BUS INTERFACES

• Bridge features
• Data flows
• Inbound transactions handling, Outbound transactions handling
• PCI bus arbitration
• PCI hierarchy configuration when operating as host

INTEGRATED DMA CONTROLLER

• Priority between the 4 channels
• Scatter / gathering
• Concurrent execution across multiple channels
• Messaging unit

INTEGRATED PROGRAMMABLE INTERRUPT CONTROLLER

• Interrupt sources
• Definition of interrupt priorities
• System critical interrupt
• Requirements to support nesting

SECURITY ENGINE

• Overview of the encryption mechanism
• Introduction to DES, 3DES and AES algorithms
• Crypto channels
• Snooping by caches
• Implementation of IPSEC

LOW SPEED PERIPHERALS

• Description of the NS16450/16550 compliant Uarts
• FIFO mode
• Flow control signal management
• I2C protocol fundamentals
• Transfer timing diagrams, SCL and SDA pins
• Transmit and receive sequence

QUICC ENGINE

SYSTEM INTERFACE AND CONNECTION TO EXTERNAL COMMUNICATION PORTS

• Serial DMA
• QUICC engine external requests
• Multi-threading
• NMSI vs TDM
• CMX registers
• Baud-rate generators

BUFFER MANAGEMENT

• Utilization of Buffer Descriptors
• Chaining descriptors into rings
• Frame boundary definition
• Interrupt management

SERIAL PERIPHERAL INTERFACE

• Introduction to SPI protocol
• SPI modes of operation in QUICC engine mode
• Transmit and receive sequence

UNIFIED COMMUNICATION CONTROLLERS

• UCC feature set
• Handling UCC interrupts
• Initialization sequence
• UCC as slow communications controllers, UART mode
• UCC for fast protocols, virtual FIFOs

UCC ETHERNET CONTROLLER

• Physical interfaces to transceiver
• Auto-negotiation
• Termination and interworking modes of operation
• IP header checksum
• FFrame filtering and address recognition
• Header parsing
• Quality of Service
• Ethernet scheduler, traffic shaper
• BD and Parameter RAM description
• Ethernet statistics, MIB

IEEE1588 ASSIST

• Overview of the IEEE1588 standard
• Timestamp unit key features
• How QuiccEngine and host software interact
• PTP frame reception
• PTP frame transmission

MULTI-CHANNEL CONTROLLER

• Comparison with MPC82XX CPM MCC
• Channel-specific HDLC parameters
• Channel extra parameters
• MCC exceptions
• MCC host commands

QUICC MULTI-CHANNEL CONTROLLER

• QMC and serial interface
• UCC Base and Global multichannel parameters
• Channel-specific HDLC parameters
• QMC exceptions
• QMC host commands

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