INTRODUCTION TO PPC464FP-H90

• Internal architecture overview
• Highlighting instruction and data paths
• Clocking
• Programming model, the 4 register groups GPRs, SPRs, DCRs and memory mapped
• CoreConnect-based SOCs

THE CORE ARCHITECTURE

• Pipeline basics
• 7-stage pipeline operation
• Speculative execution, guarded memory
• Serialization
• Cache basics
• Cache programming interface
• Process vs thread
• Memory Management Unit
• 36-bit real address space
• Translation Lookaside Buffer initialisation
• Cache control and debugging features
• Load / store buffer, speculative loads, msync and mbar instructions

BOOK E COMPLIANT CORE

• Booke E objectives
• Branch instructions
• Addressing modes
• Load / store instructions
• Semaphore management with lwarx / stwcx. Instructions
• Arithmetical and logical instructions, shift and rotate instructions
• Floating point unit, compliancy with IEEE754
• Processing denormalized FP numbers
• Floating point arithmetic instructions
• FP-to-integer and integer-to-FP casting
• The PowerPC EABI
• Cache related instructions
• 16-bit mac instructions to develop fixed point DSP algorithms
• 2-cycle multiply option
• Exception processing
• Critical versus non critical interrupts
• Syndrome registers updating when an exception is taken
• Core timers : PIT, FIT and WDT

INTEGRATED DEBUG FACILITIES

• JTAG emulator use
• The 464 instruction trace port
• Real time trace when the PowerPC core executes cached instructions
• Hardware vs software breakpoints

HARDWARE IMPLEMENTATION OF THE PPC464 CORE