ASI receiver
  The ASI receiver converts an ASI (Asynchronous Serial Interface) flow int an SPI (Synchronous Parallel Interface) flow. ASI receiver block diagram  

The MVD ASI receiver core is a drop-in module for FPGA that includes the following functions:
  • Clock/Data recovery
  • Serial/parallel Conversion
  • Sync Byte (FC Comma Detection)
  • 8B/10B decoding
  • Auto adaptation to 188/204 bytes packet Input
  • 188 bytes MPEG-TS output
  • Optional frame buffer
  • Multi mode ASI receiver
  • European standard EN50083-9 Annex B
  • Supported FPGA families: Spartan®-6, Virtex®-6/7, Kintex™-7, Artix™-7, Zynq™
  • 27MHz Single Clock
  • Supports 188 or 204 bytes packet input
  • Supports direct ASI interface (clock recovery from\par Data)
  • Supports Data Packet or Data Burst format
  • Input can be standard I/O or Transceiver I/O (GTP, GTH, GTY, GTX)
  • Single channel - support for multi channel
  • Full synthetizable RTL VHDL design (not delivered) for easy customization
  • Design delivered as Netlist

ASI receiver core may be used in applications related to DVB/MPEG-2 transport streams.
Product brief        
Data sheet        
Application note "From MPEG-TS to RF"