ASI receiver
     
         
  The Recepteur ASI receiver converts an ASI (Asynchronous Serial Interface) flow int an SPI (Synchronous Parallel Interface) flow.  
         
Description

The MVD ASI receiver core is a drop-in module that includes the following functions:
  • Clock/Data recovery
  • Serial/parallel Conversion
  • Sync Byte (FC Comma Detection)
  • 8B/10B decoding
  • Auto adaptation to 188/204 bytes packet Input
  • Baud rate measurement
  • Optional frame buffer
  • 188 bytes MPEG_ASI output

In Combined mode, no external components are needed (Equalizer and/or transformer is recommended for long cable interfaces.)

   Features
  • Multi mode ASI receiver
  • European standard EN50083-9 Annex B
  • Drop-in module for Virtex-5(tm), Virtex-4(tm) and Spartan(tm)-3/E/A FPGAs
  • Supports 188 or 204 bytes packet input
  • Supports 3 ASI interfaces Input:
    • HOTLINK (Parallel Input)
    • LVDS (separate Clock and Data Input)
    • Combined (clock recovery from Data)
  • Supports Data Packet or Data Burst format
  • Single channel - support for multi channel
  • Full synthetizable RTL VHDL design (not delivered) for easy customization
  • Netlist version available for ISE 9.2 and later versions
Applications

ASI receiver core may be used in applications related to DVB/MPEG-2 transport streams.		    
Documentation
Product brief        
Data sheet        
Application note "From MPEG-TS to RF"
           
Contact
Sales: info_cores@mvd-fpga.com
Technique: support_cores@mvd-fpga.com