Cores develops IP cores for Xilinx® Spartan®-6 and 7 series FPGA.
However, these FPGA families do not support the same interface types
for Xilinx MIG IP core.
Xilinx MIG for Spartan-6 uses slave MCB ports, while Xilinx MIG for 7 Series uses APP User Interface.
To save resources in its IP cores, MVD has chosen to implement
Spartan®-6 MCB interface instead of MIG 7 Series User interface port.
The DDR User Interface for 7 Series allows implementation of IP cores designed with multiports MCB interface in 7 Series FPGAs.
- Drop-in module for, Artix-7™, Kintex-7™,Virtex-7™ FPGAs and Zynq™ FPGAs
- slave MCB interface ports
- 32 bits data MCB interface port only
- Bidirectional or unidirectional MCB interface port
- MCB interface ports clocks synchronous or asynchronous to global clock
- One User Interface master port for 16 bits DDR 4:1 (Burst length at DDR memory is 8)
- Configurable output rate
- Full synthesizable RTL VHDL
design (not delivered) for easy customization
- Design delivered as Netlist