Description
The Input Baseband Processing
allows mixing up to 8 baseband channels.
It adds the baseband channels with full precision.
A gain register (one
per channel) can adjust the output level of each
baseband channel, and
a saturation stage avoids the overflow.
The interval frequency between channels is dependent on the
widest
bandwidth baseband input channel.
A register defines the widest bandwidth baseband input channel.
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Features
- Drop-in module for 6 Series, 7 Series and later Xilinx FPGAs
- Dual clocks (CLK: 125MHz or higher, CLKx2: 250MHz or higher)
- Dynamically user controlled output level (individual gain for each channel)
- Detection of overflow for each channel (after the individual gain)
- Overflow prevention for each channel (after the individual gain)
- Possibility to invert the spectrum for each channel
- Mute and Single tone test on each channel
- Places input channels side by side at the center RF domain (0 MHz)
- Detection of overflow at the output (after the modulation)
- Overflow prevention at the output (after the modulation)
- Add channels with full precision
- Full synthesizable RTL VHDL design (not delivered) for easy customization
- Design delivered as Netlist
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Input Baseband Processing
