ASI Transmitter
  The ASI transmitter converts an SPI (Synchronous Parallel Interface) flow into an ASI (Asynchronous Serial Interface) flow. ASI transmitter block diagram  

The MVD ASI transmitter core is a drop-in module for FPGA that includes the following functions:
  • 188 or 204 bytes MPEG-TS input
  • 8B/10B coding
  • Sync Byte (FC Comma) Insertion
  • Parallel/Serial Conversion
  • Sync Byte (FC Comma Detection)
  • Output signal polarity: normal or inverted
  • European standard EN50083-9 Annex B
  • Supported FPGA families: Spartan®-6, Virtex®-6/7, Kintex™-7, Artix™-7, Zynq™
  • 135 MHz Single clock
  • Supports 188 or 204 bytes packet input
  • Supports Data Packet or Data Burst format
  • Choice of the output signal polarity
  • Output can be standard I/O or Transceiver I/O (GTP, GTH, GTY, GTX)
  • Single channel - support for multi channel
  • Full synthesizable RTL VHDL design (not delivered) for easy customization
  • Design delivered as Netlist

ASI transmitter core may be used in applications related to DVB/MPEG-2 transport streams.
Product brief        
Data sheet        
Application note "From MPEG-TS to RF"