MPEG TS Serializer
     
         
  The MPEG TS Serializer converts a parallel MPEG TS input stream into a serial MPEG TS output stream. MPEG TS Serializer block diagram  
         
Description

The MVD MPEG TS Serializer core is a drop-in module that includes the following functions:
  • Incoming MPEG_TS clock resynchronization
  • x47 sync signal recovery
  • Parallel/Serial Conversion
  • Auto adaptation to 188/204/208 bytes packet Input
  • 188 bytes MPEG-TS serial output
  • No coding mechanism
    		   Features
    • Drop-in module for Spartan-3™, Spartan-6™, 7-Series™ FPGAs
    • Full synthesizable RTL VHDL design  (not delivered) for easy customization
    • Design delivered as Netlist
    Applications

    MVD MPEG TS Serializer may be used in applications related to DVB/MPEG-TS transport streams for Serial Data transmission between FPGA.    		    
    Documentation
    Product brief        
    Data sheet        
    Application note "From MPEG-TS to RF"
               
    Contact
    Sales: info_cores@mvd-fpga.com
    Technique: support_cores@mvd-fpga.com