RTP receiver
     
         
  Full hardware RTP receiver RTP Transmitter block diagram  
         
Description

The MVD RTP Receiver allows the reception and the treatment of a RTP stream.

The RTP receiver stores the incoming RTP packets into external memory (for example in DDR3).
During RTP packet reception, the RTP receiver analyses the different fields of the incoming RTP packet and reorder (if necessary) the incoming packet in the external memory. After the receiver has stored sufficient number of RTP packets (depending on RTP payload length), it presents
the valid data on the output bus.
  Features
  • Drop-in module for Spartan™-6, Virtex™-7, Artix™-7, Kintex™-7 and Zynq™ Xilinx FPGAs
  • Full Hardware RTP Receiver
  • Possibility to bypass RTP de-encapsulation to perform simple UDP de-encapsulation
  • External Memory is mandatory for buffering incoming RTP packets to absorb network jitter, packets loss and packets disorder
  • 8MB Memory is required by RTP Receiver
  • TS Payload only supported (for more Payload Type please contact MVD)
  • Usable in routed network with an efficient dejittering due to the field TIMESTAMP of RTP packets
  • Clock compensation for 90kHz (Clock value for TIMESTAMP Transport Stream) 100 ppm
  • Efficient reordering packet (for packet loss and packet disorder)
  • Netlist version available for ISE and VIVADO
Applications

The MVD RTP receiver can be used to receive UDP/RTP packets (or UDP packets only) on an Ethernet Network.
It may be used to receive IPTV UDP/RTP compliant stream in applications related to Multimedia transport.


Companion core

TS Jitter Cleaner to de-burst and de-jitter MPEG TS packets.

   
Documentation
Product brief        
Data sheet        
   
Contact
Sales: info_cores@mvd-fpga.com
Technique: support_cores@mvd-fpga.com