Description
The MVD Upconverter core is a
drop-in module that includes the following functions :
- An Interpolation x16 + RF Modulation per each
independent RF channel
- An Output Processing module which combines up
to 32 independent RF interpolator channels
- A clock management module
- An OSERDES module which connects the LVDS IO to
the RF DAC
- A CPU BUS to configure the parameters of the
Upconverter
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Features
- Drop-in module for Spartan-6™, Virtex-6™,
Artix-7™, Kintex-7™ and Virtex-7™ FPGAs
- Provides direct RF synthesis for baseband I-Q
signals (DC to 1.25 GHz)
- Support for 2nd and 3rd Nyquist zone for
carriers frequencies up to 3GHz+
- Includes clock
management module
- Very low FPGA resources required
- 32 or 64 MHz minimum bandwidth per RF channel
- In-band ripple < 0.2 dB and SNR > 75dB
- Carrier frequency dynamically adjustable with
sub-Hertz precision
- Dual 14-bit LVDS output busses directly tied to
AD9739/A input data pins (compatible with 11-bit for AD9737A)
- Can be modified for using others RF DAC (please
contact MVD)
- Fully synthetizable RTL VHDL design (not
delivered) for easy customization
- Design delivered as Netlists + VHDL design
example
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Digital RF Up Converter for AD9739/A DAC
