Description
The MVD DVB-S core is a drop-in module
for FPGA that includes the following
functions:
- Input data framer from DVB-SPI
source (MPEG-TS flow)
- Modulator
- Energy dispersal
- Reed Solomon encoder
- Enterleaver
- FEC convolution encoder
- Programable RRC filter
- Flexible Digital Up Sampler
- Modulator for IF output
- Output for simple DAC (14 bits)
or complex DAC (2x16bits)
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Features
DVB-S (ETS 300 421) Compliant baseband
transmitter for SatelliteModem
Termination Systems (SMTS)
- Drop-in module for
Virtex-6™,
Virtex-5™,Spartan-6™
and Spartan™-3/E/A FPGA
- Single clock (up to 140 MHz+ for
Spartan-3/6™, 180 MHz+ for
Virtex-5/6™)
- Robust SPI input (discarding
incorrect input packets)
- PCR re-stamping
- Supports programmable symbol
rates
- Programmable 1/2, 2/3, 3/4, 5/6
and 7/8 punctured FEC
- Baseband or Intermediate
frequency output for complex DAC
(2 x 16 bits)
- Single / multi channel
- Fully synthesisable RTL VHDL
design (not delivered) for easy
customization
- Design delivered as Netlist
- MER > 40dB
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DVB-S modulator -
IF output
