IPTV Receiver
  IPTV Receiver  
  An IPTV Receiver can be built from several MVD IP cores.
The IPTV Receiver extracts MPEG TS streams in UDP/RTP packets from an Ethernet link and sends them to DVB-SPI outputs
IPTV transmitter block diagram  

The IPTV Receiver is made of
  • 1 x Ethernet 100/1000 input
    (the maximum number of UDP/RTP channels depends on the FPGA resources, Ethernet speed connection and bit rate of input flows)
  • n x MPEG TS outputs (DVB-SPI)

For detailed features of each of IP cores used, please refer to their related web pages or to products briefs below.



A bi-directional IPTV Transmitter/Receiver can also be considered (see IPTV Transmitter)
In this case, the UDP/IP Stack IP can be instanced once only.

UDP/IP Stack product brief        
RTP Receiver product brief        
TS Jitter Cleaner product brief        
MDIO STA Management Interface        

Data sheets        
Sales: info_cores@mvd-fpga.com
Technique: support_cores@mvd-fpga.com